Memory modules in use in processor-based systems currently use RAM (random access memory), in particular DRAM (dynamic RAM) of several types, referred to as xc3x974 (xe2x80x9cby 4xe2x80x9d), xc3x978, xc3x9716 or xc3x9732. The designation xc3x974 means that the DRAM on a DIMM (dual in-line memory module) provides four bits of data at each clocking out of data, which in single-data read systems occurs on each rising edge of the clock on the system bus. Because current systems often use a 64-bit data width for data accesses, a DIMM with xc3x974 DRAM must have sixteen xc3x974 (i.e. sixteen four-bit) DRAM chips (or other memory devices, e.g. SDRAM, SRAM, etc.) to accommodate the full 64 bits of word length. Similarly, a xc3x978 DIMM (i.e. a DIMM with xc3x978 DRAMs) would need eight such 8-bit devices, and a DIMM with xc3x9716 DRAMs would need four such 16-bit DRAMs to make up a full 64-bit word.
Recent systems have begun to use DDR (double-data rate) DIMMs, which allow clocking of data on both rising and falling edges of the data strobes from the DIMMs, thus doubling the rate at which data transfers to and from the DIMMs can be made. DDR DIMMs in use today typically carry xc3x974, xc3x978 or xc3x9716 devices. In the JEDEC specification entitled xe2x80x9cDouble Data Rate (DDR) SDRAM Specificationxe2x80x9d (JESD79), incorporated herein by reference, the data strobe is referred to the xe2x80x9cDQSxe2x80x9d signal, and the actual data provided by or to the DRAM device is referred to as the xe2x80x9cDQxe2x80x9d signal.
Unlike synchronous DRAM devices, DDR DRAM devices use a source-synchronous clocking mechanism for data transfers between the DIMMs and the memory controller, with the memory controller of the system providing the DQS strobe as the source synchronous signal during write operations, and the DDR devices providing the DQS strobes during read operations. Thus, during write cycles, the memory controller provides both the DQ signals and the DQS strobes to the DDR DIMMs, while during a read operation the DDR DIMM provides the DQ and DQS signals.
An important design consideration for memory subsystems relates to the number of data strobes that are necessary for a given DIMM (xc3x974, xc3x978, xc3x9716, etc.) to clock out an entire 64-bit data word. Since a byte of data contains 8 bits, it is conventional with devices of at least 8-bit width (i.e. xc3x978, xc3x9716 or xc3x9732 devices, often referred to as xe2x80x9cnon-xc3x974xe2x80x9d) to clock one byte of data with one data strobe, and thus for such devices a 64-bit word requires 8 data strobes (accommodating 8 data bits each).
However, a xc3x974 device can clock out only 4 bits at a time, so an 8-bit byte requires two DQS strobes, and a 64-bit word requires 16 DQS strobes instead of the only 8 strobes for non-xc3x974 devices. In general, for any non-xc3x974 devices, including any future devices that may clock out greater numbers of bits such as 64, 128 and so on, only 8 DQS strobes will be required for a 64-bit word. It is when the number of bits that the device accommodates is less than the number of bits in a byte that the DQS strobe number increases.
In conventional DIMMs in use today, there are not enough pins available to provide an extra 8 pins in case a DIMM is carrying xc3x974 DRAM. This limit comes from physical limitations on the sizes of the DIMMs. Thus DIMMs in use today generally support only 8 data strobes.
However, DIMMs also use pins that carry signals known as data mask signals, generally including one such pin per 8 data pins. One data mask bit on a data mask pin can be used to mask (i.e., either block or pass) an entire byte of data, as needed by the system for conventional data handling purposes. It is possible to use these data mask pins as DQS strobe pins when a xc3x974 DIMM is in use, at the expense of losing the data masking functionality that would otherwise be available.
When the data mask pins are used in this way, the lower 4 bits of data (the xe2x80x9clower nibblexe2x80x9d) for a given byte may be clocked with the usual data strobe over the data strobe pin, and in that case the data mask pin for a given data byte clocks the upper 4 bits (the xe2x80x9cupper nibblexe2x80x9d) of the byte.
A problem with using the data mask pins as data strobes for xc3x974 devices is that the timing requirements for data strobes are different from those for data mask bits. Data mask bits are clocked with the actual data, i.e. they are provided to a DIMM (in the case of a write operation) substantially simultaneously with the data itself If the data mask signal and the actual data signal are not coordinated in this way, unpredictable results (such as corrupt data or incorrectly masked data) may occur.
Data strobes, on the other hand, conventionally include a preamble and a postamble period, allowing for proper setup and hold of the data-receiving component, such as the read data FIFO of a memory controller. In addition, data strobes are coordinated with a data valid window of the associated data at the receiving components. Thus, a system that accommodates both data mask signals and data strobes over a given circuit should take into account the different timing requirements of the two types of signals.
In the case of a xc3x974 device, if the data mask pins are to be used for data strobes (for the upper nibble), the timing of these upper nibble data strobes must be coordinated with the timing of the lower nibble data strobes over the usual data strobe line.
A challenge is therefore presented of providing a multimode system that can correctly execute read and write commands to memory modules of different types, namely xc3x974 and non-xc3x974, while automatically providing correct timing of data signals, data strobes, and data mask signals, depending upon which type of memory a user has installed.
A processor-based system is described that can use DIMMS carrying either xc3x974 or non-xc3x974 devices (referred to herein as xc3x974 DIMMs and non-xc3x974 DIMMs, respectively), or any combination of xc3x974 and non-xc3x974 DIMMs. A xc3x974 or non-xc3x974 device refers to a chip or circuit, such as a memory chip on board a DIMM, that clocks out data on a four-bit basis or any non-four-bit (e.g. 8-bit, 16-bit, etc.) basis, respectively.
The system includes a memory controller, which identifies each DIMM as being of a xc3x974 or a non-xc3x974 type, typically from information provided by the DIMM itself. The memory controller can receive this information dynamically (including by a hot-plugged DIMM), and thus simply plugging in the DIMM is sufficient to allow the system to handle its read and write operations correctly.
Four types of operations are contemplated: a read operation for a non-xc3x974 DIMM (or other memory component); a read operation for a xc3x974 DIMM; a write operation for a non-xc3x974 DIMM; and a write operation for a xc3x974 DIMM. In each case, the system controller controls circuit connections (including data mask pins, MUXes, gates and buses) in such a way as to pass the necessary signals to and from the DIMM for the given operation. For a non-xc3x974 DIMM, data mask signals are provided to the DIMM in a write operation, while the data mask lines are tristate for a read operation. For a xc3x974 DIMM, data strobes for the upper nibble of each byte are MUXed through the appropriate connections to (or from) the data mask pins for a read (or a write).
Multiple DIMM interface modules are provided, each of which handles some portion of an entire data word. Thus, for a 64-bit word, in one implementation eight 8-bit interface modules are used, plus an additional 8-bit module to handle ECC signals. Each module in this embodiment includes a one-bit FIFO array, and the FIFO arrays of all the modules together comprise the read data FIFO for the system.
The interface modules may be sized to handle different amounts of data and their number selected to scale the system up or down to accommodate systems using different byte or word sizes.